1. Field of the Intention
The present invention relates to a voltage generation circuit employing a capacitor and a display unit comprising this voltage generation circuit.
2. Description of the Related Art
FIG. 41 illustrates an exemplary conventional voltage generation circuit employing a capacitor. The voltage generation circuit shown in FIG. 41 comprises a capacitor (pumping capacitor) cp1, first and second p-channel MOS (metal oxide semiconductor) transistors pt1 and pt2, an inverter circuit inv1 and the like.
The first p-channel MOS transistor (driving transistor) pt1 has a drain terminal D and a gate terminal G connected to a node nd1 and a source terminal S defining a voltage output terminal 30 outputting a negative voltage VBB. The second p-channel transistor pt2 has a source terminal S connected to the node nd1, a gate terminal G connected to the inverter circuit inv1, and a drain terminal D defining a ground terminal.
The capacitor cp1 is formed by a p-channel transistor having a source terminal and a drain terminal connected in common with each other and a gate terminal G connected to the node nd1. A clock signal CLK is input in the capacitor cp1 and the inverter circuit inv1 through an input terminal 10.
The outline of operation of the voltage generation circuit having the aforementioned structure for generating the voltage (negative voltage) VBB is now described.
When the clock signal CLK goes low in logic (hereinafter simply referred to as xe2x80x9clowxe2x80x9d), the potential Vn1 of the node nd1 lowers to reach a negative voltage. When the potential Vn1 of the node nd1 lowers below the potential VBB of the source terminal S of the first p-channel MOS transistor pt1 in excess of the threshold voltage Vthp1 of the first p-channel MOS transistor pt1, the first p-channel transistor pt1 is turned on.
At this time, charges proportional to the capacitance of the capacitor cp1 flow from the source terminal S of the first p-channel MOS transistor pt1 toward the node nd1. These charges are stored in the capacitor cp1 since the second p-channel MOS transistor pt2 is in an OFF state, and the potential Vn1 of the node nd1 rises in response to these charges.
When the clock signal CLK goes high in logic (hereinafter simply referred to as xe2x80x9chighxe2x80x9d), the potential Vn1 of the node nd1 is pulled up by a level corresponding to the high level (VDD) of the clock signal CLK, to further rise.
When the clock signal CLK goes high, further, a low-level signal is input in the second p-channel MOS transistor pt2 through the inverter circuit inv1, to turn on the second p-channel MOS transistor pt2. At this time, the charges stored in the capacitor cp1 are extracted to the ground terminal (GND), and the potential Vn1 of the node nd1 lowers.
Thus, the charges are pumped from the source terminal S of the first p-channel MOS transistor pt1 to the ground terminal (GND) every cycle of the clock signal CLK, thereby rendering the voltage of the source terminal S of the first p-channel MOS transistor pt1 negative.
FIG. 42 shows a voltage generation circuit known as an example improving the pumping efficiency of the aforementioned conventional voltage generation circuit. This voltage generation circuit uses two conventional voltage generation circuits described above, and applies clock signals CLK and /CLK inverted in phase to each other to terminals of pumping capacitors cp1 and cp2 respectively thereby improving the pumping efficiency thereof and reducing the time for attaining a prescribed negative voltage.
While the aforementioned conventional voltage generation circuit effectively generates the voltage (negative voltage) VBB with a simple structure, the theoretical value of the achieved negative voltage (VBB) is (xe2x88x92VDD+Vthp1+Vthp2) in FIG. 41 and (xe2x88x92VDD+Vthp1) in FIG. 42, which is less than the maximum logical value (xe2x88x92VDD) by the threshold voltage (Vthp1, Vthp2) of the first and second p-channel MOS transistors pt1 and pt2.
As the output negative voltage VBB lowers, further, the potential difference between the source terminal S of the first p-channel MOS transistor pt1 and the node nd1, i.e., the gate-to-source voltage of the first p-channel MOS transistor pt1 reduces to lower the drivability of the first p-channel MOS transistor pt1.
In recent years, a voltage generation circuit having high current drivability is required in view of current drivability necessary for controlling word lines of a DRAM (dynamic random access memory) with a negative bias or in view of reduction in power consumption and attainment of operating margins of pixel transistors in a liquid crystal display unit or the like. However, the aforementioned conventional voltage generation circuit cannot sufficiently satisfy such requirements due to the low current drivability.
An object of the present invention is to provide a voltage generation circuit capable of obtaining a high voltage with high current drivability and a display unit comprising this voltage generator.
A voltage generation circuit according to an aspect of the present invention has a capacitor and generates a prescribed voltage through a node connected to a first terminal of the capacitor, and further comprises an n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a p-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while gate terminals of the n-channel transistor and the p-channel transistor are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor, and the other one of the two clock signals is applied to the gate terminals connected in common.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the n-channel transistor serving as a driving transistor. When generating a negative voltage, for example, the driving transistor is reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistor can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistor is employed as the driving transistor, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistor, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistor with the n-channel transistor, further, the element areas of the transistors can be reduced.
The voltage generation circuit is preferably formed on a P-type semiconductor substrate having a triple well structure, the n-channel transistor preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the p-channel transistor preferably includes a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, and the capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit may be formed on an N-type semiconductor substrate having a double well structure, the n-channel transistor may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the p-channel transistor may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, and the capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit may be formed on a glass substrate, an active layer of each of the n-channel transistor and the p-channel transistor may be formed from a semiconductor layer formed on the glass substrate, and at least one electrode of the capacitor may be formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The voltage generation circuit preferably further comprises an inverter circuit for forming the two clock signals on the basis of a single clock signal.
In this case, the two clock signals can be formed from the single clock signal, whereby the structure of an external circuit can be simplified as compared with the case of employing the two clock signals from the first. Further, the voltage can be effectively generated due to a delay effect through the inverter circuit.
The two clock signals preferably have a period when both of the two clock signals go low in logic in phase inversion.
In this case, the two clock signals have the period when both of the same go low in logic, whereby the potential of the node can be set to a positive voltage after reliably turning off the driving transistor, for example, for effectively generating the negative voltage.
The voltage generation circuit may further comprise a logic circuit for forming the two clock signals on the basis of a single clock signal, and a delay circuit adjusting a period so that the two clock signals have a period when both of the two clock signals go low in logic in phase inversion.
In this case, a pair of clock signals having the period when both of the two clock signals go low in logic in phase inversion can be readily and automatically produced on the basis of the single clock signal.
A voltage generation circuit according to another aspect of the present invention has first and second capacitors and generates a prescribed voltage through first and second nodes connected to first terminals of the first and second capacitors respectively, and further comprises a first n-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a second n-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a first p-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining a reference potential terminal, and a second p-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor are connected in common and connected to the second node, a gate terminal of the second n-channel transistor and the gate terminal of second p-channel transistor are connected in common and connected to the first node, the output terminals of the first and second n-channel transistors are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the first capacitor, and the other one of the two clock signals is applied to a second terminal of the second capacitor.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the first and second n-channel transistors serving as driving transistors. When generating a negative voltage, for example, the driving transistors are reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistors can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistors are employed as the driving transistors, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistors, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistors with the n-channel transistors, further, the element areas of the transistors can be reduced.
In addition, pumping operation is performed every half cycle of the clock signals, whereby pumping can be more efficiently performed for increasing the speed for reaching the target output voltage.
The voltage generation circuit is preferably formed on a P-type semiconductor substrate having a triple well structure, each of the first and second n-channel transistors preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, each of the first and second p-channel transistors preferably includes a MOSFET formed on an N-type well to which the clock signal is applied for obtaining its back gate potential, the first capacitor preferably includes a p-channel transistor separately formed on an N-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor preferably includes a p-channel transistor separately formed on an N-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a P-type semiconductor substrate having a triple well structure, each of the first and second n-channel transistors may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, each of the first and second p-channel transistors may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, the first capacitor may include a p-channel transistor separately formed on an N-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor may include a p-channel transistor separately formed on an N-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a P-type semiconductor substrate having a triple well structure, each of the first and second n-channel transistors may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, each of the first and second p-channel transistors may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, the first capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a P-type semiconductor substrate having a double well structure, each of the first and second n-channel transistors may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, each of the first and second p-channel transistors may include a MOSFET formed on an N-type well to which a positive potential is applied for obtaining its back gate potential, the first capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on an insulator film formed on a silicon substrate, an active layer of each of the first and second n-channel transistors and the first and second p-channel transistors may be formed from a semiconductor layer formed on the insulator film, and at least one electrode of each of the first and second capacitors is formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The voltage generation circuit may be formed on a glass substrate, an active layer of each of the first and second n-channel transistors and the first and second p-channel transistors may be formed from a semiconductor layer formed on the glass substrate, and at least one electrode of each of the first and second capacitors may be formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The voltage generation circuit preferably further comprises an inverter circuit for forming the two clock signals on the basis of a single clock signal.
In this case, the two clock signals can be formed from the single clock signal, whereby the structure of an external circuit can be simplified as compared with the case of employing the two clock signals from the first. Further, the voltage can be effectively generated due to a delay effect through the inverter circuit.
The two clock signals preferably have a period when both of the two clock signals go low in logic in phase inversion.
In this case, the two clock signals have the period when both of the two clock signals go low in logic, whereby the potential of the node can be set to a positive voltage after reliably turning off the driving transistors, for example, for effectively generating the negative voltage.
The voltage generation circuit may further comprise a logic circuit for forming the two clock signals on the basis of a single clock signal and a delay circuit adjusting a period so that the two clock signals have a period when both of the two clock signals go low in logic in phase inversion.
In this case, a pair of clock signals having the period when both of the two clock signals go low in logic in phase inversion can be readily and automatically produced on the basis of the single clock signal.
A voltage generation circuit according to still another aspect of the present invention has a capacitor and generates a prescribed voltage through a node connected to a first terminal of the capacitor, and further comprises a first n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a second n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor and the other one of the two clock signals is applied to a gate terminal of the first n-channel transistor.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the first n-channel transistor serving as a driving transistor. When generating a negative voltage, for example, the driving transistor is reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistor can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistor is employed as the driving transistor, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistor, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistor with the n-channel transistor, further, the element areas of the transistors can be reduced.
The voltage generation circuit is preferably formed on a P-type semiconductor substrate having a triple well structure, the first n-channel transistor preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the second n-channel transistor preferably includes a MOSFET formed on a P-type well to which the node is connected for obtaining its back gate potential, and the capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit may be formed on an N-type semiconductor substrate having a double well structure, the first n-channel transistor may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the second n-channel transistor may include a MOSFET formed on a P-type well to which the node is connected for obtaining its back gate potential, and the capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the node.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the first and second n-channel transistors is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of the capacitor is preferably formed from an n-type region formed on part of the semiconductor layer.
The voltage generation circuit preferably further comprises an inverter circuit for forming the two clock signals on the basis of a single clock signal.
In this case, the two clock signals can be formed from the single clock signal, whereby the structure of an external circuit can be simplified as compared with the case of employing the two clock signals from the first. Further, the voltage can be effectively generated due to a delay effect through the inverter circuit.
The two clock signals preferably have a period when both of the two clock signals go low in logic in phase inversion.
In this case, the two clock signals have the period when both of the two clock signals go low in logic, whereby the potential of the node can be set to a positive voltage after reliably turning off the driving transistors, for example, for effectively generating the negative voltage.
The voltage generation circuit may further comprise a logic circuit for forming the two clock signals on the basis of a single clock signal and a delay circuit adjusting a period so that the two clock signals have a period when both of the two clock signals go low in logic in phase inversion.
In this case, a pair of clock signals having the period when both of the two clock signals go low in logic in phase inversion can be readily and automatically produced on the basis of the single clock signal.
A voltage generation circuit according to a further aspect of the present invention has first and second capacitors and generates a prescribed voltage through first and second nodes connected to first terminals of the first and second capacitors respectively, and further comprises a first n-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a second n-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a third n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the first node with the other one of the source terminal and the drain terminal defining a reference potential terminal, and a fourth n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the second node with the other one of the source terminal and the drain terminal defining a reference potential terminal, while the output terminals of the first and second n-channel transistors are connected in common, a gate terminal of the first n-channel transistor is connected to the second node, a gate terminal of the second-n-channel transistor is connected to the first node, one of two clock signals inverted in phase to each other is applied to a second terminal of the first capacitor, and the other one of the two clock signals is applied to a second terminal of the second capacitor.
The voltage generation circuit can obtain an output voltage not influenced by the threshold voltage Vth of the first and second n-channel transistors serving as driving transistors. When generating a negative voltage, for example, the driving transistors are reliably turned on also when the output negative voltage lowers, whereby the drivability of the driving transistors can be sufficiently secured regardless of the value of the negative voltage. Further, the n-channel transistors are employed as the driving transistors, whereby the operating speed of the voltage generation circuit can be increased as compared with the case of employing the p-channel transistors, and the drivability can be increased. When securing ability equivalent to that of the p-channel transistors with the n-channel transistors, further, the element areas of the transistors can be reduced.
In addition, pumping operation is performed every half cycle of the clock signals, whereby pumping can be more efficiently performed for increasing the speed for reaching the target output voltage.
The voltage generation circuit is preferably formed on a P-type semiconductor substrate having a triple well structure, each of the first and second n-channel transistors preferably includes a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the third n-channel transistor preferably includes a MOSFET formed on a P-type well to which the first node is connected for obtaining its back gate potential, the fourth n-channel transistor preferably includes a MOSFET formed on a P-type well to which the second node is connected for obtaining its back gate potential, the first capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor preferably includes an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a P-type semiconductor substrate having a double well structure, each of the first and second n-channel transistors may include a MOSFET formed on a P-type well to which the output terminal is connected for obtaining its back gate potential, the third n-channel transistor may include a MOSFET formed on a P-type well to which the first node is connected for obtaining its back gate potential, the fourth n-channel transistor may include a MOSFET formed on a P-type well to which the second node is connected for obtaining its back gate potential, the first capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the first node, and the second capacitor may include an n-channel transistor separately formed on a P-type well with a source terminal and a drain terminal connected in common and a gate terminal connected to the second node.
The voltage generation circuit may be formed on a glass substrate, an active layer of each of the first to fourth n-channel transistors may be formed from a semiconductor layer formed on the glass substrate, and at least one electrode of each of the first and second capacitors may be formed from an n-type region formed on part of the semiconductor layer.
The voltage generation circuit preferably further comprises an inverter circuit for forming the two clock signals on the basis of a single clock signal.
In this case, the two clock signals can be formed from the single clock signal, whereby the structure of an external circuit can be simplified as compared with the case of employing the two clock signals from the first. Further, the voltage can be effectively generated due to a delay effect through the inverter circuit.
The two clock signals preferably have a period when both of the two clock signals go low in logic in phase inversion.
In this case, the two clock signals have the period when both of the two clock signals go low in logic, whereby the potential of the node can be set to a positive voltage after reliably turning off the driving transistors, for example, for effectively generating the negative voltage.
The voltage generation circuit may further comprise a logic circuit for forming the two clock signals on the basis of a single clock signal and a delay circuit adjusting a period so that said two clock signals have a period when both of the two clock signals go low in logic in phase inversion.
In this case, a pair of clock signals having the period when both of the two clock signals go low in logic in phase inversion can be readily and automatically produced on the basis of the single clock signal.
A display unit according to a further aspect of the present invention comprises a plurality of display pixels arranged on intersections between a plurality of scan lines and a plurality of data lines in the form of a matrix, a plurality of active switching elements provided for the respective display pixels for controlling a voltage applied to the display pixels, a scan line driving circuit scanning the plurality of scan lines while applying a driving voltage for activating the plurality of active switching elements and a voltage generation circuit outputting a prescribed voltage to the scan line driving circuit, while the voltage generation circuit has a capacitor and generates the prescribed voltage through a node connected to a first terminal of the capacitor, the voltage generation circuit further includes an n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a p-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, gate terminals of the n-channel transistor and the p-channel transistor are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor, and the other one of the two clock signals is applied to the gate terminals connected in common.
When the voltage generation circuit generates a negative voltage in the display unit, power consumption can be reduced and operating margins of the active switching elements can be increased by employing a voltage from a prescribed negative voltage to half a power supply voltage, for example, as a voltage applied to the scan lines. Further, the capacitance of an external capacitor generally provided outside the display unit as an element for storing negative charges can be so reduced that this capacitor can be miniaturized or omitted.
When the display unit is a liquid crystal display unit generally required to reach a negative voltage as soon as possible upon power supply, the aforementioned voltage generation circuit can quickly supply the negative voltage due to its effective pumping operation. When AC-driving liquid crystal electrodes opposed to each other for reducing power consumption, the gate potential of pixel transistors can be set to a lower negative potential due to the large achieved negative voltage regardless of the threshold voltage of transistors, whereby the aforementioned voltage generation circuit can prevent data leak and reduce power consumption. Further, the display quality of the liquid crystal display unit can be improved by loading the voltage generation circuit having a large driving current (drivability) on the liquid crystal display unit.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the n-channel transistor and the p-channel transistor is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of the capacitor is preferably formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The display unit preferably further comprises a level conversion circuit stepping up/converting the levels of signals applied to the voltage generation circuit as the clock signals. In this case, the voltage generation circuit can properly generate a voltage such as a prescribed negative voltage, for example, required by the display unit with the aforementioned level conversion circuit.
A display unit according to a further aspect of the present invention comprises a plurality of display pixels arranged on intersections between a plurality of scan lines and a plurality of data lines in the form of a matrix, a plurality of active switching elements provided for the respective display pixels for controlling a voltage applied to the display pixels, a scan line driving circuit scanning the plurality of scan lines while applying a driving voltage for activating the plurality of active switching elements and a voltage generation circuit outputting a prescribed voltage to the scan line driving circuit, while the voltage generation circuit has first and second capacitors and generates the prescribed voltage through first and second nodes connected to first terminals of the first and second capacitors respectively, the voltage generation circuit further includes a first n-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a second n-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a first p-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining a reference potential terminal and a second p-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining a reference potential terminal, a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor are connected in common and connected to the second node, a gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor are connected in common and connected to the first node, the output terminals of the first and second n-channel transistors are connected in common, one of two clock signals inverted in phase to each other is applied to a second terminal of the first capacitor, and the other one of the two clock signals is applied to a second terminal of the second capacitor.
When the voltage generation circuit generates a negative voltage in the display unit, power consumption can be reduced and operating margins of the active switching elements can be increased by employing a voltage from a prescribed negative voltage to half a power supply voltage, for example, as a voltage applied to the scan lines. Further, the capacitance of an external capacitor generally provided outside the display unit as an element for storing negative charges can be so reduced that this capacitor can be miniaturized or omitted.
When the display unit is a liquid crystal display unit generally required to reach a negative voltage as soon as possible upon power supply, the aforementioned voltage generation circuit can quickly supply the negative voltage due to its effective pumping operation. When AC-driving liquid crystal electrodes opposed to each other for reducing power consumption, the gate potential of pixel transistors can be set to a lower negative potential due to the large achieved negative voltage regardless of the threshold voltage of transistors, whereby the aforementioned voltage generation circuit can prevent data leak and reduce power consumption. Further, the display quality of the liquid crystal display unit can be improved by loading the voltage generation circuit having a large driving current (drivability) on the liquid crystal display unit.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the first and second n-channel transistors and the first and second p-channel transistors is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of each of the first and second capacitors is formed from an n-type region or a p-type region formed on part of the semiconductor layer.
The display unit preferably further comprises a level conversion circuit stepping up/converting the levels of signals applied to the voltage generation circuit as the clock signals. In this case, the voltage generation circuit can properly generate a voltage such as a prescribed negative voltage, for example, required by the display unit with the aforementioned level conversion circuit.
A display unit according to a further aspect of the present invention comprises a plurality of display pixels arranged on intersections between a plurality of scan lines and a plurality of data lines in the form of a matrix, a plurality of active switching elements provided for the respective display pixels for controlling a voltage applied to the display pixels, a scan line driving circuit scanning the plurality of scan lines while applying a driving voltage for activating the plurality of active switching elements and a voltage generation circuit outputting a prescribed voltage to the scan line driving circuit, while the voltage generation circuit has a capacitor and generates a prescribed voltage through a node connected to a first terminal of the capacitor, the voltage generation circuit further includes a first n-channel transistor having one of a source terminal and a drain terminal connected to the node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage and a second n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the node with the other one of the source terminal and the drain terminal defining a reference potential terminal, one of two clock signals inverted in phase to each other is applied to a second terminal of the capacitor, and the other one of the two clock signals is applied to a gate terminal of the first n-channel transistor.
When the voltage generation circuit generates a negative voltage in the display unit, power consumption can be reduced and operating margins of the active switching elements can be increased by employing a voltage from a prescribed negative voltage to half a power supply voltage, for example, as a voltage applied to the scan lines. Further, the capacitance of an external capacitor generally provided outside the display unit as an element for storing negative charges can be so reduced that this capacitor can be miniaturized or omitted.
When the display unit is a liquid crystal display unit generally required to reach a negative voltage as soon as possible upon power supply, the aforementioned voltage generation circuit can quickly supply the negative voltage due to its effective pumping operation. When AC-driving liquid crystal electrodes opposed to each other for reducing power consumption, the gate potential of pixel transistors can be set to a lower negative potential due to the large achieved negative voltage regardless of the threshold voltage of transistors, whereby the aforementioned voltage generation circuit can prevent data leak and reduce power consumption. Further, the display quality of the liquid crystal display unit can be improved by loading the voltage generation circuit having a large driving current (drivability) on the liquid crystal display unit.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the first and second n-channel transistors is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of the capacitor is preferably formed from an n-type region formed on part of the semiconductor layer.
The display unit preferably further comprises a level conversion circuit stepping up/converting the levels of signals applied to the voltage generation circuit as the clock signals. In this case, the voltage generation circuit can properly generate a voltage such as a prescribed negative voltage, for example, required by the display unit with the aforementioned level conversion circuit.
A display unit according to a further aspect of the present invention comprises a plurality of display pixels arranged on intersections between a plurality of scan lines and a plurality of data lines in the form of a matrix, a plurality of active switching elements provided for the respective display pixels for controlling a voltage applied to the display pixels, a scan line driving circuit scanning the plurality of scan lines while applying a driving voltage for activating the plurality of active switching elements and a voltage generation circuit outputting a prescribed voltage to the scan line driving circuit, while the voltage generation circuit has first and second capacitors and generates the prescribed voltage through first and second nodes connected to first terminals of the first and second capacitors respectively, the voltage generation circuit further includes a first n-channel transistor having one of a source terminal and a drain terminal connected to the first node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a second n-channel transistor having one of a source terminal and a drain terminal connected to the second node with the other one of the source terminal and the drain terminal defining an output terminal outputting the prescribed voltage, a third n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the first node with the other one of the source terminal and the drain terminal defining a reference potential, and a fourth n-channel transistor having one of a source terminal and a drain terminal as well as a gate terminal connected to the second node with the other one of the source terminal and the drain terminal defining a reference potential terminal, the output terminals of the first and second n-channel transistors are connected in common, a gate terminal of the first n-channel transistor is connected to the second node, a gate terminal of the second n-channel transistor is connected to the first node, one of two clock signals inverted in phase to each other is applied to a second terminal of the first capacitor, and the other one of the two clock signals is applied to a second terminal of the second capacitor.
When the voltage generation circuit generates a negative voltage in the display unit, power consumption can be reduced and operating margins of the active switching elements can be increased by employing a voltage from a prescribed negative voltage to half a power supply voltage, for example, as a voltage applied to the scan lines. Further, the capacitance of an external capacitor generally provided outside the display unit as an element for storing negative charges can be so reduced that this capacitor can be miniaturized or omitted.
When the display unit is a liquid crystal display unit generally required to reach a negative voltage as soon as possible upon power supply, the aforementioned voltage generation circuit can quickly supply the negative voltage due to its effective pumping operation. When AC-driving liquid crystal electrodes opposed to each other for reducing power consumption, the gate potential of pixel transistors can be set to a lower negative potential due to the large achieved negative voltage regardless of the threshold voltage of transistors, whereby the aforementioned voltage generation circuit can prevent data leak and reduce power consumption. Further, the display quality of the liquid crystal display unit can be improved by loading the voltage generation circuit having a large driving current (drivability) on the liquid crystal display unit.
The voltage generation circuit is preferably formed on a glass substrate, an active layer of each of the first to fourth n-channel transistors is preferably formed from a semiconductor layer formed on the glass substrate, and at least one electrode of each of the first and second capacitors is formed from an n-type region formed on part of the semiconductor layer.
The display unit preferably further comprises a level conversion circuit stepping up/converting the levels of signals applied to the voltage generation circuit as the clock signals. In this case, the voltage generation circuit can properly generate a voltage, such as a prescribed negative voltage, for example, required by the display unit with the aforementioned level conversion circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.